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ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 18 features ? 168-pin unbuffered 8-byte dual in-line memory module ? 32mx64/72 synchronous dram dimm ? two speed sorts: ? -260 and -360 for pc100 applications ? inputs and outputs are lvttl (3.3v) compatible ? single 3.3v 0.3v power supply ? single pulsed ras interface ? sdrams have 4 internal banks ? module has 2 physical banks ? fully synchronous to positive clock edge ? data mask for byte read/write control ? auto refresh (cbr) and self refresh ? automatic and controlled precharge commands ? programmable operation: - cas latency: 2, 3 - burst type: sequential or interleave - burst length: 1, 2, 4, 8, full-page (full- page supports sequential burst only) - operation: burst read and write or multiple burst read with single write ? suspend mode and power down mode ? 12/10/2 addressing (row/column/bank) ? 4096 refresh cycles distributed across 64ms ? serial presence detect ? card size: 5.25" x 1.375" x 0.158" max ? gold contacts ? sdrams in tsop type ii package description ibm13n32644jca / ibm13n32734jca are unbuf- fered 168-pin synchronous dram dual in-line memory modules (dimms) which are organized as 32mx64 and 32mx72 high-speed memory arrays and are configured as two 16mx64/72 physical banks. the dimms use sixteen (32mx64) or eigh- teen (32mx72) 16mx8 sdrams in 400mil tsop ii packages. the dimms achieve high-speed data- transfer rates of up to 100mhz by employing a prefetch/pipeline hybrid architecture that supports the jedec 1n rule while allowing very low burst power. the -260 and -360 speed sort dimms are compati- ble with the intel pc100 sdram unbuffered dimm specification. all control, address, and data input/output circuits are synchronized with the positive edge of the exter- nally supplied clock inputs. all inputs are sampled at the positive edge of each externally supplied clock (ck0 - ck3). internal oper- ating modes are defined by combinations of ras, cas, we, s0- s3, dqmb, and cke0-cke1 signals. a command decoder initiates the necessary timings for each operation. a 14-bit address bus accepts address information in a row/column multiplexing arrangement. prior to any access operation, the cas latency, burst type, burst length, and burst operation type must be programmed into the dimm by address inputs a0-a9 during the mode register set cycle. the dimm uses serial presence detects imple- mented via a serial eeprom using the two pin iic protocol. the first 128 bytes of serial pd data are used by the dimm manufacturer. the last 128 bytes are available to the customer. all ibm 168-pin dimms provide a high-performance, flexible 8-byte interface in a 5.25 long space-saving footprint. related products include both edo dram and sdram unbuffered dimms in both non-parity x64 and ecc-optimized x72 configurations. card outline 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back) .
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 18 09k3540.f38351 8/99 pin description ck0 - ck3 clock inputs dq0 - dq63 data input/output cke0 - cke1 clock enables cb0 - cb7 check bit data input/output ras row address strobe dqmb0 - dqmb7 data mask cas column address strobe v dd power (3.3v) we write enable v ss ground s0, s1, s2, s3 chip selects nc no connect a0 - a9, a11 address inputs scl serial presence detect clock input a10 /ap address input/autoprecharge sda serial presence detect data input/output ba0, ba1 sdram bank address inputs sa0-2 serial presence detect address inputs wp serial presence detect write protect input pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 22 cb1 106 cb5 43 v ss 127 v ss 64 v ss 148 v ss 2 dq0 86 dq32 23 v ss 107 v ss 44 nc 128 cke0 65 dq21 149 dq53 3 dq1 87 dq33 24 nc 108 nc 45 s2 129 s3 66 dq22 150 dq54 4 dq2 88 dq34 25 nc 109 nc 46 dqmb2 130 dqmb6 67 dq23 151 dq55 5 dq3 89 dq35 26 v dd 110 v dd 47 dqmb3 131 dqmb7 68 v ss 152 v ss 6 v dd 90 v dd 27 we 111 cas 48 nc 132 nc 69 dq24 153 dq56 7 dq4 91 dq36 28 dqmb0 112 dqmb4 49 v dd 133 v dd 70 dq25 154 dq57 8 dq5 92 dq37 29 dqmb1 113 dqmb5 50 nc 134 nc 71 dq26 155 dq58 9 dq6 93 dq38 30 s0 114 s1 51 nc 135 nc 72 dq27 156 dq59 10 dq7 94 dq39 31 nc 115 ras 52 cb2 136 cb6 73 v dd 157 v dd 11 dq8 95 dq40 32 v ss 116 v ss 53 cb3 137 cb7 74 dq28 158 dq60 12 v ss 96 v ss 33 a0 117 a1 54 v ss 138 v ss 75 dq29 159 dq61 13 dq9 97 dq41 34 a2 118 a3 55 dq16 139 dq48 76 dq30 160 dq62 14 dq10 98 dq42 35 a4 119 a5 56 dq17 140 dq49 77 dq31 161 dq63 15 dq11 99 dq43 36 a6 120 a7 57 dq18 141 dq50 78 v ss 162 v ss 16 dq12 100 dq44 37 a8 121 a9 58 dq19 142 dq51 79 ck2 163 ck3 17 dq13 101 dq45 38 a10/ap 122 ba0 59 v dd 143 v dd 80 nc 164 nc 18 v dd 102 v dd 39 ba1 123 a11 60 dq20 144 dq52 81 wp 165 sa0 19 dq14 103 dq46 40 v dd 124 v dd 61 nc 145 nc 82 sda 166 sa1 20 dq15 104 dq47 41 v dd 125 ck1 62 nc 146 nc 83 scl 167 sa2 21 cb0 105 cb4 42 ck0 126 nc 63 *cke1 147 nc 84 v dd 168 v dd note: all pin assignments are consistent for all 8-byte unbuffered versions. check bits (cb0 - cb7) are applicable only to the x72 dimm; for the x64 dimm these pins are no connects (nc). * cke1 is terminated with a 10k ohm pullup resistor. ordering information part number organization clock cycle leads dimension power IBM13N32644JCA-260T 16mx64 10ns gold 5.25 " x 1.375 " x 0.158 " 3.3v ibm13n32644jca-360t ibm13n32734jca-260t 16mx72 ibm13n32734jca-360t
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 32mx64 sdram dimm block diagram (2 bank, 16mx8 sdrams) s0 s1 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d0 dqmb0 dqm d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dqm i/o 0 i/o 1 i/o 2 i/o 3 d1 dqm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqm i/o 0 i/o 1 i/o 2 i/o 3 d2 dqm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqm i/o 0 i/o 1 i/o 2 i/o 3 d3 dqm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqm i/o 0 i/o 1 i/o 2 i/o 3 d4 dqmb4 dqm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqm i/o 0 i/o 1 i/o 2 i/o 3 d5 dqm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dqm i/o 0 i/o 1 i/o 2 i/o 3 d6 dqm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqm i/o 0 i/o 1 i/o 2 i/o 3 d7 dqm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb7 v dd v ss d0 - d15 d0 - d15 a0 - a11 a0-a11: sdrams d0 - d15 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda * all resistor values are 10 ohms except as shown. * s2 s3 ras ras: sdrams d0 - d15 cas cas: sdrams d0 - d15 cke0 cke: sdrams d0 - d7 we we: sdrams d0 - d15 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cke1 cke: sdrams d8 - d15 v dd 10k note: exact dq wiring may differ from that shown above. ba0 a13/bs0: sdrams d0 - d15 ck0 clk: sdrams d0 - d1, d4 - d5, 3.3pf cap ck1 clk: sdrams d8 - d9, d12 - d13, 3.3pf cap ck2 clk: sdrams d2 - d3, d6 - d7, 3.3pf cap ck3 clk: sdrams d10 - d11, d14 - d15, 3.3pf cap ba1 a12/bs1: sdrams d0 - d15 wp 47k 0.1 m f .33 m f
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 18 09k3540.f38351 8/99 32mx72 sdram dimm block diagram (2 bank, 16mx8 sdrams) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d0 dqmb0 dqm d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 dqm i/o 0 i/o 1 i/o 2 i/o 3 d1 dqm d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dqm i/o 0 i/o 1 i/o 2 i/o 3 d3 dqm d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dqm i/o 0 i/o 1 i/o 2 i/o 3 d4 dqm d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dqm i/o 0 i/o 1 i/o 2 i/o 3 d5 dqmb4 dqm d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dqm i/o 0 i/o 1 i/o 2 i/o 3 d6 dqm d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dqm i/o 0 i/o 1 i/o 2 i/o 3 d7 dqm d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb6 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dqm i/o 0 i/o 1 i/o 2 i/o 3 d8 dqm d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqmb7 v dd v ss d0 - d17 d0 - d17 a0 - a11 a0-a11: sdrams d0 - d17 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d2 dqm d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 * * all resistor values are 10 ohms except as shown. ras ras: sdrams d0 - d17 cas cas: sdrams d0 - d17 cke0 cke: sdrams d0 - d8 we we: sdrams d0 - d17 s0 s1 s2 s3 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cke1 cke: sdrams d9 - d17 v dd 10k ba0 a13/bs0: sdrams d0 - d17 ck0 clk: sdrams d0 - d2, d5 - d6 ck1 clk: sdrams d9 - d11, d14 - d15 ck2 clk: sdrams d3 - d4, d7 - d8, 3.3pf cap. ck3 clk: sdrams d12 - d13, d16 - d17, 3.3pf cap. note: exact dq wiring may differ from that shown above. ba1 a12/bs1: sdrams d0 - d17 wp 47k 0.1 m f .33 m f
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 input/output functional description symbol type signal polarity function ck0 - ck3 input pulse positive edge the system clock inputs. all of the sdram inputs are sampled on the rising edge of their associated clock. cke0, cke1 input level active high activates the sdram clk signals when high and deactivates them when low. by deacti- vating the clocks, cke0/cke1 low initiates the power down mode, suspend mode, or the self refresh mode. s0 - s3 input pulse active low enables the associated sdram command decoder when low and disables the com- mand decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. ba0, ba1 input level selects which sdram bank is to be active. a0 - a9 a10/ap a11 input level during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then ba0/ba1 are used to define which bank to pre- charge. dq0 - dq63, cb0 - cb7 input output level data and check bit input/output pins operate in the same manner as on conventional drams. dqmb0 - dqmb7 input pulse active high the data input/output mask places the dq buffers in a high impedance state when sam- pled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. sa0 - sa2 input level address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda input output level serial data. bidirectional signal used to transfer data into and out of the serial presence detect eeprom. since the sda signal is open drain/open collector at the eeprom, a pull-up resistor is required on the system board. scl input pulse serial clock. used to clock all serial presence detect data into and out of the eeprom. since the scl signal is inactive in the high state, a pull-up resistor is recommended on the system board. wp input level active high hardware write protect. when wp is active, writing to the eeprom array is inhibited. on the dimm, this input is connected to the eeprom write protect input and is also tied to ground through a 47k ohm pull-down resistor. v dd , v ss supply power and ground for the module.
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 18 09k3540.f38351 8/99 serial presence detect (part 1 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram 04 3 number of row addresses on assembly 12 0c 4 number of column addresses on assembly 9 0a 5 number of dimm banks 2 02 6 - 7 data width of assembly 32m x 64 x64 48 32m x 72 x72 00 8 voltage interface level of this assembly lvttl 01 9 sdram device cycle time at cl=3 10.0ns a0 10 sdram device access time from clock at cl=3 6.0ns 60 1 11 dimm configuration type 32m x 64 non-parity 00 32m x 72 ecc 02 12 refresh rate/type sr/1x(15.625us) 80 13 primary sdram device width x8 08 14 error checking sdram device width 32m x 64 n/a 00 32m x 72 x8 08 15 sdram device attr: min clk delay, random col access 1 clock 01 16 sdram device attributes: burst lengths supported 1,2,4,8, full page 8f 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latencies supported 2, 3 06 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 0 01 21 sdram module attributes unbuffered 00 22 sdram device attributes: general wr-1/rd burst, precharge all, auto-precharge, v dd +/- 10% 0e 23 minimum clock cycle at cl=2 -260 10.0ns a0 -360 15.0ns f0 24 maximum data access time (t ac ) from clock at cl=2 -260 6.0ns 60 1 -360 9.0ns 90 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data access time (t ac ) from clock at cl=1 n/a 00 27 minimum row precharge time (t rp ) 20ns 14 28 minimum row active to row active delay (t rrd ) 20ns 14 1. see the ac output load circuit in the ac characteristics section below 2. cc = checksum data byte, 00-ff (hex) 3. r = alphanumeric revision code, a-z, 0-9 4. rr = ascii coded revision code byte r 5. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex) 6. ww = binary coded decimal week code, 01-52 (decimal) ? 01-34 (hex) 7. ss = serial number data byte, 00-ff (hex)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 29 minimum ras to cas delay (t rcd ) 20ns 14 30 minimum ras pulse width (t ras ) 50ns 32 31 module bank density 128mb 20 32 address and command setup time before clock 2.0ns 20 33 address and command hold time after clock 1.0ns 10 34 data input setup time before clock 2.0ns 20 35 data input hold time after clock 1.0ns 10 36 - 61 reserved undefined 00 62 spd revision 1.2a 12 63 checksum for bytes 0 - 62 checksum data cc 2 64 - 71 manufacturers jedec id code ibm a400000000000000 72 module manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 module part number 32m x 64, -260 ascii 13n32644jcr-260t 31334e33323634344a43rr 2d323630542020 3, 4 32m x 64, -360 ascii 13n32644jcr-360t 31334e33323634344a43rr 2d333630542020 32m x 72, -260 ascii 13n32734jcr-260t 31334e33323733344a43rr 2d323630542020 32m x 72, -360 ascii 13n32734jcr-360t 31334e33323733344a43rr 2d333630542020 91 - 92 module revision code r plus ascii blank rr20 3, 4 93 - 94 module manufacturing date year/week code yyww 5, 6 95 - 98 module serial number serial number ssssssss 7 99 - 125 reserved undefined 00 126 module supports this clock frequency 100 mhz 64 127 attributes for clock frequency defined in byte 126 -260 ck0, ck1, ck2, ck3, cl3, cl2, concurrent ap f7 -360 ck0, ck1, ck2, ck3, cl3, concurrent ap f5 128 - 255 open for customer use unde?ned 00 serial presence detect (part 2 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. see the ac output load circuit in the ac characteristics section below 2. cc = checksum data byte, 00-ff (hex) 3. r = alphanumeric revision code, a-z, 0-9 4. rr = ascii coded revision code byte r 5. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex) 6. ww = binary coded decimal week code, 01-52 (decimal) ? 01-34 (hex) 7. ss = serial number data byte, 00-ff (hex)
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 18 09k3540.f38351 8/99 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v1 v in input voltage sdram devices -0.3 to v dd +0.3 serial pd device -0.3 to +6.5 v out output voltage sdram devices -0.3 to v dd +3.3 serial pd device -0.3 to +6.5 t a operating temperature (ambient) 0 to +70 c1 t stg storage temperature -55 to +125 c1 p d power dissipation x64 6.5 w1 x72 7.3 i out short circuit output current 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a = 0 to 70?c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v 1, 2 v il input low voltage -0.3 0.8 v 1, 3 1. all voltages referenced to v ss . 2. v ih (max) = v dd + 1.2v for pulse width 5ns. 3. v il (min) = v dd - 1.2v for pulse width 5ns. capacitance (t a = 25 c, f=1mhz, v dd = 3.3v 0.3v) symbol parameter organization units x64 max. x72 max. c i1 input capacitance (a0 - a9, a10/ap, a11, ba0, ba1, ras, cas, we) 104 112 pf c i2 input capacitance (cke0 - cke1) 54 58 pf c i3 input capacitance ( s0 - s3) 30 33 pf c i4 input capacitance (ck0 - ck3) 40 40 pf c i5 input capacitance (dqmb0 - dqmb7) 17 21 pf c i6 input capacitance (sa0 - sa2, scl, wp) 9 9 pf c io1 input/output capacitance (dq0 - dq63, cb0 - cb7) 17 17 pf c io2 input/output capacitance (sda) 11 11 pf
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 dc output load circuit output characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) symbol parameter x64 x72 units notes min. max. min. max. i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v ras, cas, we, a0-a9, a10/ap, a11, ba0, ba1 -80 +80 -90 +90 m a ck0, ck1 -20 +20 -25 +25 ck2, ck3 -20 +20 -20 +20 cke0, cke1 -40 +40 -45 +45 s0, s1 -20 +20 -25 +25 s2, s3 -20 +20 -20 +20 dqmb1, 5 -10 +10 -15 +15 dqmb0, 2, 3, 4, 5, 6, 7 -10 +10 -10 +10 dq0 - 63 -10 +10 -10 +10 cb0 - 7 0 0 -10 +10 sa0, sa1, sa2, scl, sda -10 +10 -10 +10 wp -10 +50 -10 +50 i o(l) output leakage current (d out is disabled, 0.0v v out v dd ) dq0 - 63 -10 +10 -10 +10 m a cb0 - 7 0 0 -10 +10 sda -10 +10 -10 +10 v oh output level (lvttl) output h level voltage (i out = -2.0ma) 2.4 - 2.4 - v1 v ol output level (lvttl) output l level voltage (i out = +2.0ma) - 0.4 - 0.4 1. see dc output load circuit. output 1200 w 50pf 3.3 v 870 w v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 18 09k3540.f38351 8/99 operating, standby, and refresh currents (t a = 0 to +70 c, v dd = 3.3v 0.3v) parameter symbol test condition speed/organization units notes -260, -360/x64 -260, -360/x72 operating current t rc = t rc (min), t ck = min active-precharge command cycling without burst operation i cc1 1 bank operation 960 1080 ma 1, 3, 4 precharge standby current in power down mode i cc2p cke0, cke1 v il (max), t ck = min, s0 - s3 =v ih (min) 16 18 ma 2 i cc2ps cke0, cke1 v il (max), t ck = infinity, s0 - s3 =v ih (min) 16 18 ma 2 precharge standby current in non- power down mode i cc2n cke0, cke1 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 560 630 ma 2, 5 i cc2ns cke0, cke1 3 v ih (min), t ck = infinity, s0 - s3 =v ih (min) 160 180 ma 2, 6 no operating current (active state: 4 bank) i cc3n cke0, cke1 3 v ih (min), t ck = min, s0 - s3 =v ih (min) 640 720 ma 2, 5 i cc3p cke0, cke1 v il (max), t ck = min, s0 - s3 =v ih (min) (power down mode) 160 180 ma 2, 7 burst operating current i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data, bl = 4 1040 1170 ma 1, 4, 8 auto (cbr) refresh current i cc5 t ck = min, cbr command cycling 1800 2025 ma 1 self refresh current i cc6 cke0, cke1 0.2v 32 36 ma 2 serial pd device standby current i sb v in = gnd or v dd 30 30 m a9 serial pd device active power sup- ply current i cca scl clock frequency = 100khz 1 1 ma 10 1. the speci?ed values are for one dimm bank in the speci?ed mode, and the other dimm bank in active standby (i cc3n ). 2. the speci?ed values are for both dimm banks operating in the speci?ed mode. 3. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to three times during t rc (min). 4. the specified values are obtained with the output open. 5. input signals are changed once during three clock cycles. 6. input signals are stable. 7. active standby current will be higher if clock suspend is entered during a burst read cycle (add 1ma per dq). 8. input signals are changed once during t ck(min) . 9. v dd = 3.3v. 10. as follows: ? input pulse levels v dd x 0.1 to v dd x 0.9 ? input and output timing levels v dd x 0.5 ? output load 1 ttl gate and cl=100p f
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 ac characteristics (t a = 0 to +70 c, v dd = 3.3v 0.3v) 1. an initial pause of 200 m s, with dqmb0-7 and cke0-cke1 held high, is required after power-up. a pre- charge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set operation. 2. the transition time is measured between v ih and v il (or between v il and v ih ). 3. in addition to meeting the transition rate speci?cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.40v crossover point 5. ac measurements assume t t =1.2 ns. ac characteristics diagrams output input clock t oh t setup t hold t ac t lz 1.4v 1.4v 1.4v t t t ckh t ckl output 50pf z o = 50 w ac output load circuit v il v ih
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 18 09k3540.f38351 8/99 clock and clock enable parameters symbol parameter -260 -360 units notes min. max. min. max. t ck3 clock cycle time, cas latency = 3 10 1000 10 1000 ns t ck2 clock cycle time, cas latency = 2 10 1000 15 1000 ns 1 t ac3 (a) clock access time, cas latency = 3 ns 2 t ac2 (a) clock access time, cas latency = 2 ns 2 t ac3 (b) clock access time, cas latency = 3 66ns3 t ac2 (b) clock access time, cas latency = 2 69ns3 t ckh clock high pulse width 33ns4 t ckl clock low pulse width 33ns4 t ces clock enable set-up time 22ns t ceh clock enable hold time 11ns t sb power down mode entry time 0 10 0 10 ns t t transition time (rise and fall) 0.5 10 0.5 10 ns 1. for -360 sort, 66mhz clock: cas latency = 2. 2. access time is measured at 1.4v. see ac characteristics: notes: 1, 2, 3, 4, 5 and load circuit a. 3. access time is measured at 1.4v. see ac characteristics: notes: 1, 2, 3, 6, 7 and load circuit b. 4. t ckh is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max). common parameters symbol parameter -260 -360 units notes min. max. min. max. t cs command setup time 2 2 ns t ch command hold time 1 1 ns t as address and bank select set-up time 2 2 ns t ah address and bank select hold time 1 1 ns t rcd ras to cas delay 20 20 ns 1 t rc bank cycle time 70 70 ns 1 t ras active command period 50 100000 50 100000 ns 1 t rp precharge time 20 20 ns 1 t rrd bank to bank delay time 20 20 ns 1 t ccd cas to cas delay time 1 1 clk 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 mode register set cycle symbol parameter -260 -360 units notes min. max. min. max. t rsc mode register set cycle time 2 2 clk 1 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). read cycle symbol parameter -260 -360 units notes min. max. min. max. t oh data out hold time 2.5 2.5 ns t lz data out to low impedance time 00ns t hz3 data out to high impedance time 3 6 3 6 ns 1 t hz2 data out to high impedance time 3 6 3 8 ns 1 t dqz dqm data out disable latency 22 clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. refresh cycle symbol parameter -260 -360 units notes min. max. min. max. t ref refresh period 64 64 ms 1 t srex self refresh exit time 10 10 ns 1. 4096 auto refresh cycles. write cycle symbol parameter -260 -360 units min. max. min. max. t ds data in set-up time 22ns t dh data in hold time 11ns t dpl data input to precharge 10 10 ns t dqw dqm write mask latency 0 - 0 - clk
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 18 09k3540.f38351 8/99 presence detect read and write cycle symbol parameter min max unit notes f scl scl clock frequency 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 functional description and timing diagrams refer to the ibm 128mb synchronous dram die revision a data sheet, document 33l8019, for the func- tional description and timing diagrams for sdram operation. refer to the ibm application notes serial presence detect on memory dimms and sdram presence detect definitions for the serial presence detect functional description and timings. all ac timing information refers to the timings at the sdram devices.
ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 18 09k3540.f38351 8/99 layout drawing r 1.00 .0393 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 detail a scale 4/1 millimeters inches 66.68 2.63 6.35 .250 42.18 1.661 1.27 pitch .050 1.00 width .039 see detail a 1.375 (2) 0 3.18 .1255 133.35 5.25 127.35 5.014 .118 3.0 (2x) 4.00 .157 .700 1780 front 34.925 * note: on x72 module only 4.01 .158 max. side .004 1.27 0.10 .050 + _ + _ 5.95 .234 min. * 131.35 5.171
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 18 ibm13n32644jca ibm13n32734jca 32m x 64/72 two-bank unbuffered sdram module 09k3540.f38351 8/99 revision log rev contents of modi?cation 7/99 initial release. 8/99 removed preliminary
intern ational business machines corp.1999 copyright printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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